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HyperLib 1997 Winter - Disc 1
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Z80ppc 160.sit
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z80.reference.h
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1995-04-13
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/* Z80 Emulator: header file
Copyright (C) 1995 G.Woigk
This file is part of Mac Spectacle and it is free software
See application.c for details
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*/
/* override normal references to use separate variables and procedures for reference engine
all references in PPC Z80 engine to zreg, CORE, etc. now go to ref_zreg, REF_CORE, etc. instead!
caveat: #undef zreg, CORE, etc. after #including this file somewhere else !!!
*/
#define zreg ref_zreg // 2nd register set for Z80_Ref()
#define CORE REF_CORE // 2nd core for Z80_Ref()
#define Do_Output(A,B) No_Output(A,B) // ignore out's of Z80_Ref()
#define Do_Input(A) Do_Input(A) // hint: don't poll events between input of Z80_T() and Z80_Ref()
#define write_to_rom(A,B) Dont_Write(A,B) // don't write to ROM; Z80_T() shouldn't write to ROM too
// ----- The Z80 RAM --------------------------------------------------------------
extern Char *CORE; // RAM & ROM of Z80
// ----- Flag tables ----------------------------------------------------------------
extern Char zlog_flags[256]; // convert: A register -> z80 flags with V=parity and C=0
extern Char mlog_flags[256]; // convert: A register -> m68 flags with V=parity and C=0
extern Char z80flags[256]; // convert: m68 flag byte -> Z80 flag byte
extern Char m68flags[256]; // convert: Z80 flag byte -> m68 flag byte
// ----- Z80 registers on entry and return of Z80() -----------------------------------
#define pair union _pair
pair { Char *ptr;
struct { Short corebase; Short reg; } rr;
struct { Short corebase; Char hi,lo; } r;
};
#define regs struct _regs
regs { pair BC,DE,HL,IX,IY,IP,RP;
Short BC2,DE2,HL2;
Char AA2,A2,aa,A; // A2 & A occupy ONE long register inside Z80()
Char FF2, F2, ff, F; // F2 & F occupy ONE long register inside Z80()
Char I, // hi byte of irpt vector
irptcmd; // lo byte of irpt vector read from data bus: 0xff
Char IFF1,IFF2;
Char EXIT,WUFF; // watchdog flag & nmi/irpt flags
Char R; // 7 bit DRAM refresh counter
Char IM; // interrupt mode: 0 ... 2
long CYCLES; // processor T states (count down for interrupt)
long TOTAL; // T states since start of Z80 (overflows approx. every 20')
};
extern regs zreg; // all z80 registers and flip flops are stored in this struct
// ----- definitions to ease the use of the z80 registers
#define ra zreg.A // Z80() uses register variable 'a'
#define rf zreg.F // Z80() uses register variable 'f'
#define ra2 zreg.A2
#define rf2 zreg.F2
#define abc zreg.BC.ptr
#define bc zreg.BC.rr.reg
#define rb zreg.BC.r.hi
#define rc zreg.BC.r.lo
#define ade zreg.DE.ptr
#define de zreg.DE.rr.reg
#define rd zreg.DE.r.hi
#define re zreg.DE.r.lo
#define ahl zreg.HL.ptr
#define hl zreg.HL.rr.reg
#define rh zreg.HL.r.hi
#define rl zreg.HL.r.lo
#define aix zreg.IX.ptr
#define ix zreg.IX.rr.reg
#define xh zreg.IX.r.hi
#define xl zreg.IX.r.lo
#define aiy zreg.IY.ptr
#define iy zreg.IY.rr.reg
#define yh zreg.IY.r.hi
#define yl zreg.IY.r.lo
#define apc zreg.IP.ptr
#define pc zreg.IP.rr.reg
#define pch zreg.IP.r.hi
#define pcl zreg.IP.r.lo
#define asp zreg.RP.ptr
#define sp zreg.RP.rr.reg
#define sph zreg.RP.r.hi
#define spl zreg.RP.r.lo
#define bc2 zreg.BC2
#define de2 zreg.DE2
#define hl2 zreg.HL2
#define irpt_cmd zreg.irptcmd // read this interrupt vector / 1-byte instruction from bus
#define disabled 0x00 // irpt flags
#define enabled 0xFF // irpt flags
// bits in zreg.WUFF:
#define is_nmi 0x80 // non maskable interrupt: handled inside Z80()
#define is_irpt 0x7F // normal interrupt counter: handled inside Z80()
// ----- Return values of Z80() -----------------------------------------------------
#define watchdog_irpt 0 // watchdog exception (used for screen update & Mac OS event polling)
#define illegal_instr 1 // a not implemented instruction has been executed
#define halt_instr 2 // halt instruction executed
#define rst0_instr 3 // rst0 instruction executed
#define irpt_error 4 // not supported interrupt mode/instruction
// ----- Procedures -------------------------------------------------------------------
short Z80_Ref ( );
short CB_Instruction();
short ED_Instruction();
// ----- The following procedures must be supplied by the application program ---------------
extern Do_Output ( Short addr, Char n ); // Output byte to port
Char Do_Input ( Short addr ); // Input byte from port
extern write_to_rom ( Short A, Char N); // Write byte to ROM (or don't)
#define cc zreg.CYCLES
#define store_cc
#define load_cc
#define time(N) cc-=N-4 // T cycles for instruction
#define more(N) cc-=N // adjust T cycles after use of time()
#define exit(n) return(n)
#define wl (Char)w // access low byte of w
#define wh (w>>8) // access high byte of w
#define wml (Char)wm // access low byte of wm
#define wmh (wm>>8) // access high byte of wm